Energy Minimization through Micro-architecture Techniques using Pipelining on Multicore CPUs

With the ever-growing use of computers and rapid growth in chip fabrication technology, the performance of CPU doubled approximately every 18 months by Moore’s law and CPU clock speed increased exponentially for better performance guarantees. The advancement in IC technology led to the increase in number of chips on a processor which in turn resulted in more power consumption. The basic power consumption and its associated factors in a processor are determined by the number of transistors in a core. In addition, the architectural design efficiency plays a vital role when designing an energy efficient processor or in multicore designs. In High performance computing, everyone needs a processor with low power consumption and high performance. The techniques used for performance enhancements will increase more power consumption. In order to achieve high performance processor with low power consumption, I propose a new pipelining micro-architecture level technique to reduce the number of optimum pipeline stages in a processor which will decrease the number of latches in turn decreases the energy consumption without compromising the performance of the processor. 1 Overview of field of Research Energy consumption is one of the key factors in the development of ever growing computer systems. Low powered high performance devices are in greater demand in IT industry. There are number of ways are already exists that can minimize the energy consumption of a CPU. They are process level, application level, custom design, and micro-architecture level design. Deeper pipeline increases the power consumption. In order to accomplish low power, the proposed research work, a micro-architecture level design technique called pipelining is used to reduce the energy consumption of the multicore CPUs. 1.1 Current Research Issues on Multicore Processors • Performance enhancement: Performance enhancement of multicore have many bottlenecks like multi threaded interaction, Memory bandwidth problem, resourceful data handling. Getting optimal multicore application performance lots of research going on to address these issues. Performance enhancement and low power consumption is the key research area in multicore environment. • Cache Coherency problem: In computing , cache coherence refers to consistency of data stored in local caches of a shared resources.When a client system maintains cahces of common memory resources problem may arise with inconsistent data. This causes memory latency in turn increases energy consumption. There are lots of research work is going in cache coherency problem in multicore . Figure 1: Cache coherency • Power Management: Performance no longer dominates the design objectives: chip fabrication costs and fault tolerance, power efficiency,and heat dissipation have become critical considerations.As cores are simplified, power consumption decreases linearly which is a major advantage of multicore CPUs. Increased power efficiency and reduced heat generation permit the integration of more cores into a single CPU. • With the tradeoff that the power budget for the interconnect increases with the number of cores.Multicore CPUs also provide greater options for power management as CMP cores can be individually power-tuned by being powered off or run at a lower frequency when system load is light. In order to overcome these, modern processors have power savings circuit implementation with modern cooling technology. • Scalability ( How to provide computational performance within the number of processor cores) Power, scale the performance within the power budget. • Reliability, How to scale up the performance for future processor technology. • Verification of multicore programming. • Parallel programmability ( How to reduce programming effort on multicore processor). • Latency and bandwidth (How to manage system latency and scale up the memory bandwidth upto the computational performance ). • Heterogeneity, approach to keep power within the envelop of available technology. • Resource management. 1.2 Literature Survey There has been tremendous growth in chip fabrication technology for computing systems. The trade-off between performance and power has a vital role in this growth. Processor design techniques such as ASIC, custom design, process design and micro-architecture design are used to achieve high speed with less power consumption. With the scaling advancement in IC Technology, the amount of power the chip dissipates per unit area is increased, due to increase in transistor density . Power consumption is the major factor even for high-end computing. Among these, the most common power affecting factors are ASIC and micro-architectural design level constraints. In ASIC design and fabrication technology, power consumption depends on the duration the chip is active. Power efficiency can be achieved through logical circuit gating, process technology, process variation, voltage scaling, cell and wire sizing [15]. A significant research has been carried out on power reduction. There is power reduction in voltage scaling by using 2*4 parallel data paths [1]. Clock gating is the technique which increases power efficiency when the chip is on. Reducing the supply voltage, reduces the subthreshold leakage current and gate-oxide tunneling leakage [7] [11]. The voltage drop across sleep transistors takes substantial power due to high capacitance [14]. ASIC design techniques adopt CMOS logic for combinational logic circuits. Pass Transistor Logic (PTL) has high speed and low power logic style [2]. Using logic styles like PTL, PMOS, CMOS needs more careful cell design and layout. An alternative way of reducing the power gap between EDA (Electronic Design Automation) and CMOS logic is to adopt custom design flow. Downsizing the transistors gives a linear reduction in capacitance, and thus a reduction in dynamic and leakage power. High speed combinational logic style on a critical path is needed to enhance the speed [4]. However, when the performance of the pipeline is considered, the CMOS circuitry is preferred to have high power consumption per operation. All these logic circuitry have high leakage power than CMOS logic circuits. In order to avoid leakage through NMOS transistors, it is required to keep PMOS transistor alive [16], with a trade-off between power and clock gate sizing, i.e, to reduce the delay, increase the gate sizes on a critical path and capacitance on a chip. The logic circuit delay can be determined by the factors such as logic style, layout, process technology and process variation. Reducing the P/N ratio provides smaller reduction in delay and thus a substantial reduction in power consumption [13]. At 325MHz of clock frequency, power compiler was able to reduce the power consumption by 26 % and reduce the chip area by 12 % for no delay penalty. By using deeper submicron technologies the power consumption and power per unit area is reduced [10]. There are number of sources of process variations such as channel width, transistor wire length and width, proximity effects and wafer defects that affect the power consumption.The other factor in custom design is wire length. Optimizing the wire width size reduces the clock net power, thus saves the total power [5]. The power consumption due to interconnection has significant impact on wire length. The wire delay and IR drop in wire could be avoided by using copper wires.[12]. Narendra et al showed that silicon-on-insulator (SOI) was 14 to 28% faster than bulk CMOS for some 0.18um gates. The total power was 30% lower at the same delay, but the leakage was 1.2 to 20% larger. Micro-architectural design choices and algorithms also reduce the power by an order of magnitude [6]. Low power consumption is essential for high performance computing, embedded applications and scientific applications. A substantial number of research work on power reduction in multicore has already been carried out by many researchers. My research work focuses mainly on low power consumption of multicore processors through microarchitecture design techniques. 2 Relation and relevance for own research Power consumption is one of the key factors in the development of ever-growing computing systems. Power aware processors are in great demand for various high end application domains, like wireless sensor networks, mobile embedded devices, and in many scientific applications that are required to achieve high performance. Many design techniques have been adopted to reduce the power consumption of the processors. They are